Me and a friend have been messing around with his Casio keyboard (AT-1) and successfully did a LTC-1799 mod on the DSP clock. First we tried to put it on the DAC's clock in, but that resulted in very ugly harsh noise. This is because the DAC in the AT-1 (upd6376cx) expects a 16 bit word from the serial bus (from the DSP LSI), every 16 clock cycles, so when we give the DAC an asynchronous clock signal it will result in a digital garbage sound.
Then we put the LTC-1799 on the DSP clock in, and that resulted in very nice crashy circuit bendy sound. Mission success!
But our first experiment with the DAC had us thinking: What if we could sequence the serial data from the DSP to hit the DAC, in tandem with a new divided clock, we send to the DAC? Would we get a cheap time stretch effect or would we get a variable pitch? We had to find out!
So we designed a PCB which is meant to take the clock from the AT-1 and divide it by n (n can be equal to 8) using a 4017 decade counter, that clock signal is then passed on to the AT-1.
For the serial data sequencer we first convert the serial data to parallel using two 40595 shift registers. The parallel data then is fed into an array of four FIFO latch registers that are controlled by two 4161 ripple counters and some logic (one for the undivided clock domain, and one for the divided clock domain). The output from the FIFO array is then converted from parallel to serial by a 74hc165 PISO shift register and passed on to the DAC in the AT-1.
This is the theory at least. Before we start to test the circuit (we need to spend a not insignificant amount of money on a good breadboard and components) we thought to ask knowledgeable people on this forum to kindly look at our schematic and give critique and in the case of our complete misunderstanding, angry comments.
This could very probably be done very easy on a modern microcontroller, but where is the sport in that? but also in this case we feel it makes sense to do it discretely with DIP IC's.
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Then we put the LTC-1799 on the DSP clock in, and that resulted in very nice crashy circuit bendy sound. Mission success!
But our first experiment with the DAC had us thinking: What if we could sequence the serial data from the DSP to hit the DAC, in tandem with a new divided clock, we send to the DAC? Would we get a cheap time stretch effect or would we get a variable pitch? We had to find out!
So we designed a PCB which is meant to take the clock from the AT-1 and divide it by n (n can be equal to 8) using a 4017 decade counter, that clock signal is then passed on to the AT-1.
For the serial data sequencer we first convert the serial data to parallel using two 40595 shift registers. The parallel data then is fed into an array of four FIFO latch registers that are controlled by two 4161 ripple counters and some logic (one for the undivided clock domain, and one for the divided clock domain). The output from the FIFO array is then converted from parallel to serial by a 74hc165 PISO shift register and passed on to the DAC in the AT-1.
This is the theory at least. Before we start to test the circuit (we need to spend a not insignificant amount of money on a good breadboard and components) we thought to ask knowledgeable people on this forum to kindly look at our schematic and give critique and in the case of our complete misunderstanding, angry comments.
This could very probably be done very easy on a modern microcontroller, but where is the sport in that? but also in this case we feel it makes sense to do it discretely with DIP IC's.
Statistics: Posted by SysEx Addict — Thu Feb 22, 2024 8:21 am