Original digital delay has no CPU. Sampling and memory addressing is synchronous with a clock pulse. To change delay time, you either change the clock frequency or the size of the memory. A sample is read out to a DAC, then a new sample is written from the ADC before incrementing the memory address. Address is from a binary counter treated as a circular buffer which wraps back to zero at maximum or resets from a higher address bit for shorter delay.
With a CPU able to address the delay memory, a different system is available. Samples can be read separately from an address the same or behind the current new sample write position, and that difference is the delay time. Delay time can be from zero (a new sample passed direct to the DAC) up to the maximum memory size, and additional read "taps" are possible with additional DACs or by mixing tap reads digitally to a single DAC. Feedback can be mixed in with new ADC reads digitally too. The delay time can be modulated by an LFO waveform table, which provides an offset to the read address from the current address. The sampling rate and addressing are synchronous and fixed.
With a CPU able to address the delay memory, a different system is available. Samples can be read separately from an address the same or behind the current new sample write position, and that difference is the delay time. Delay time can be from zero (a new sample passed direct to the DAC) up to the maximum memory size, and additional read "taps" are possible with additional DACs or by mixing tap reads digitally to a single DAC. Feedback can be mixed in with new ADC reads digitally too. The delay time can be modulated by an LFO waveform table, which provides an offset to the read address from the current address. The sampling rate and addressing are synchronous and fixed.
Statistics: Posted by JimY — Fri Mar 22, 2024 2:10 pm